Network processors (NPs) are employed in many of today's communications products, as opposed to traditional application specific integrated circuits (ASICs) or field programmable gate array (FPGA) fixed hardware, primarily because the architecture of these processors provides the flexibility of a software based feature set solution with the high performance of ASICs. Network processors utilize parallel processing or serial pipelines and are programmable like general purpose microprocessors, but are optimized for packet processing operations required by data packet network communication devices.
A typical architecture of a network processor includes multiple core processors (CP), also referred to as packet processing engines, a plurality of interworking first-in-first-out (FIFO) queues implemented in memory, and one or more memory buses (MB) interconnecting the core processors with the FIFO queues and external memories. Packets are stored in the interworking FIFO queues between processing operations performed on the packets by various core processors. The core processors, memory buses, and interworking FIFO queues are hereinafter referred to collectively as network processor resources.
Transient traffic bursts or a constant high rate of small packets that cannot be handled by a network processor due to physical limitations of the network processor resources may lead to silent traffic loss. The traffic lost in this case would typically be random and indiscriminate, that is, packets of any traffic priority could be affected. Such loss may result in loss of data services, which could be difficult to detect and debug in a live deployment.
Therefore, a way of monitoring resources of a network processor to detect a congestion condition in the resources is desired.